Huge openings In MNC - VLSI ASIC domain - Verification, Physical Designing and Implementation (1-10yrs)
Hi Dear Candidate,
We have huge openings in VLSI ASIC domain - Verification, Physical Designing and Implementation.
Please please forward this mail to all your friend and colleagues ( Its Request )
Send me your profile with below details (Must) to Prashanth.benaka@gmail.com
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VLSI ASIC - Verification, Physical Designing – Linked in Group
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Current Location:
Willing to relocate Location:
Current CTC:
Expected CTC:
Applying Position:
Notice Period:
Small note about experience:
Key Skills :
Tools Names:
Company: MNC
Work Locations: Bangalore , Noida , Chennai and if candidate excellent Onsite also
Below find the positions :
Intermediate Verification Engineer
Experience : 3-6yrs of ASIC/FPGA verification experience
Should have done at least 1 ASIC project
Educational Qualification
BE/BTech/ME/MTech
Language : Should have experience in of specman in live projects
Verification skill : create tests; debug/analyze them to conclusion in HVL verification environment
Communication : Should posses good oral and written communication skills
Should be able to mentor/guide junior team members
Senior Verification Engineer
Experience : 6-10 yrs of ASIC/FPGA verification experience
Should have done multiple ASIC project
Educational Qualification : BE/BTech/ME/MTech
Language : Should have experience in of specman in live projects
Verification skill : Should be able to make the HVL verification environments, testplan strategy, testcases etc.,
Knowledge on coverage (code + functional) essential.
Should have worked in communication projects – Ethernet/SONET/OTN
Communication : Should posses good oral and written communication skills
Should be able to manage a 3-5 member team, conducting their appraisals and identifying training plans
ASIC DFT Engineer
Experience : B Tech 3 to 5 years
M Tech 2 to 4 years
Educational Qualification : BE/BTech/ME/MTech
Role & Responsibilities : Generation and verification of Scan at speed and stuck at vectors.
Generation and verification of Boundary scan vectors
Generation and verification of Interconnect vectors
Generation and verification of RAMBIST vectors
Mapping the vectors to device level and verify
Track the scan coverage of each module and ensure they are as per norms
Skills Required : Scan insertion and Scan Stitching
Worked for DFT scan vector gen and sim for atleast 2 years
Responsibility of owning SCAN and JTAG methodologies of Device
Formal verification
Experience in Unix environment
Tools: Cadence ET, Synopsys Tetramax, Mentor Fastscan.
Advanced knowledge of SCAN, Memory Bist and JTAG, IEEE 1149, IEEE P1500, Solving LEC issues
ASIC Implementation Engineer
Experience : B Tech 6 to 8 years
M Tech 4 to 6 years
Educational Qualification : BE/BTech/ME/MTech
Role & Responsibilities: Full chip synthesis and timing analysis
Block level synthesis and Static timing analysis
Full chip DFT architecture
Scan insertion and Scan Stitching
Formal verification
Experience in Unix environment
Skills Required : Building a Full chip synthesis and timing analysis
Timing closure for at least chip
Resolving Timing closure issues in Deep Sub Micron chips
ASIC implementation and team leadership
Tools: RTL Compiler, Primetime or Goldtime
VLSI/System Design/SoC Functional Verification in DataCom, Storage, Communication domains
Thanks and Regards
Prashanth
HR Business Consultant
Email : Prashanth.benaka@gmail.com
Bangalore , India
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